The best way to clock a converter is with internal clock, using a good fundamental frequency crystal (third order types are more jittery), and locating the crystal properly (good ground to the AD ample hold and so on). You now have a low jitter clock inside the machine.
What happens when you get a stand alone “almost no jitter clock”? You look AT THE OUTPUT CONNECTOR of that “super clock box” and it generally can work as well as the internal crystal clock Now take a cable and hook it to the AD chassis. Now you have to go through some electronic circuit to receive the clock. At this point, you have accumulated a lot more jitter (I can list half a dozen causes).
Well, this is not the end of the road. The big one is the PLL circuit. Unlike the internal clock (fixed crystal case), you have a crystal that can be pulled up or down by some amount, we call it a VCXO (voltage controlled crystal oscillator). There is some circuitry in there that keeps comparing the incoming external clock rate to the VCXO, and makes the proper adjustment on an ongoing basis…
What is more steady? A mediocre internal crystal implementation is going to outdo even a good external clock implementation.
But there are times and reasons to use external clocks. For example, if one needs to sync many chassis…
It is true that the PLL does better when fed a less jittery clock, but that is just a tiny portion of the overall issue. As Bob stated, most of the burden is on the PLL. A Good PLL, inside the AD chassis should clean most of the jitter out.
. Bedankt voor de input! 
